// ================================
//	MBOC115 / TSOC117 Combinational Test
//		poly-core: shared ram access test
//		(c) 2025	1YEN Toru
// ================================
asm		"mcoc_irom.mem"
incl	"mcoc115.incl"
# ================================


// ================================
// r4=cpu id
movfc	r4,sr
cendw	r4
lsri	r4,sreg_b_id0-8
andi	r4,sreg_id_15>>sreg_b_id0
cmpi	r4,sreg_id_0>>sreg_b_id0
beq		tstfail							// single cpu system
cmpi	r4,sreg_id_15>>sreg_b_id0
bne		pcnt+4
ldbiu	r4,sreg_id_1>>sreg_b_id0
bra		start_test


start_test:

// ================================
// shared ram access
ldbiu	r1,0
ldwi	r7,ramtop
cmpi	r4,sreg_id_1>>sreg_b_id0
bne		pcnt+2
stw		[r7],r1							// flag clear
ldwi	r5,ramtop
add		r5,r4
add		r5,r4
sra_loop:
// count up
addi	r1,1
stw		[r5],r1
// break condition
cmpi	r1,32
blo		pcnt+2
stw		[r7],r1
// end of loop
ldw		r0,[r7]
cmpi	r0,0
beq		sra_loop
sra_break:

// halt if cpu#!=3
cmpi	r4,sreg_id_3>>sreg_b_id0
beq		pcnt+4
pause
bra		pcnt-4

// print calculated data
ldwi	r5,princtl
ldwi	r0,(asc_spc<<8)|prin_nld
stw		[r5],r0
ldwi	r5,princhr
ldbiu	r1,asc_lf
ldwi	r6,prindec
// repeat
ldbiu	r2,0
rept	1+14							// flag + cores
ldw		r0,[r7]
addi	r7,2
stw		[r6],r2
stw		[r6],r0
stw		[r5],r1
addi	r2,1
endr


// ================================
tstpass:
ldwi	r0,simpass						// pass: LED=blue
bra		tstfnsh
tstfail:
ldwi	r0,simfail						// fail: LED=red
tstfnsh:
ldwi	r7,simfnsh
stw		[r7],r0
bra		pcnt-2
nop
// ================================

