// ================================
//	Nihonium + BUSC
//		long word access test: ram marching test (even word address)
//		(c) 2023	1YEN Toru
// ================================
asm		"mcoc_irom.mem"
incl	"mcoc115.incl"
# ================================
# constants
equ		mch_top,ramtop+0				// march: start address
equ		mch_inc,0x0004					// march: address increment
equ		mch_end,mch_top+64*mch_inc		// march: end address
# ================================


// initialize
sesr	sreg_b_nh
movfc	r0,sr
lsfti	r0,-sreg_b_nh
andi	r0,1
beq		tstfail

// print title
ldwi	r7,princhr
ldwi	r1,lab_prn_title
prn_loop:
ldb		r0,[r1]
cmpi	r0,0
beq		prn_break
addi	r1,1
stb		[r7],r0
bra		prn_loop

prn_title:
dats	"RAM Marching test\n\0"
prn_break:

// ================================
// marching test
// ================================
//		r7=addr
//		r6=end of addr
//		r0=0x0000_0000
//		r1=0xffff_ffff
//		r2=inc
//		r3=temporal data
ldwi	r6,mch_end
ldbiu	r0,0x00
mov		r1,r0
not		r1
ldwi	r2,mch_inc

// ================================
// write all 0
ldwi	r7,mch_top
wr0_loop:
stl		[r7],r0
add		r7,r2
cmp		r7,r6
blo		wr0_loop

// ================================
// read 0, write 1
ldwi	r7,mch_top
r0w1_loop:
ldl		r3,[r7]
stl		[r7],r1
add		r7,r2
cmp		r3,r0
bne		mch_fail
cmp		r7,r6
blo		r0w1_loop

// ================================
// read 1, write 0
ldwi	r7,mch_top
r1w0_loop:
ldl		r3,[r7]
stl		[r7],r0
add		r7,r2
cmp		r3,r1
bne		mch_fail
cmp		r7,r6
blo		r1w0_loop

// ================================
// read all 0
ldwi	r7,mch_top
rd0_loop:
ldl		r3,[r7]
add		r7,r2
cmp		r3,r0
bne		mch_fail
cmp		r7,r6
blo		rd0_loop

mch_pass:
bra		tstpass

mch_fail:
bra		tstfail


// ================================
tstpass:
ldwi	r0,simpass						// pass: LED=blue
bra		tstfnsh
tstfail:
ldwi	r0,simfail						// fail: LED=red
tstfnsh:
ldwi	r7,simfnsh
stw		[r7],r0
bra		pcnt-2
nop
// ================================