// ================================
// Moscovium
//		general register bank test program
//		(c) 2021	1YEN Toru
// ================================
asm		"asm_mcvm.v"
#incl	"mcoc115.incl"
# ================================
equ		ramtop,0x5000
# simulation finish condition
equ		simfnsh,0xf028
equ		simpass,0x8006
equ		simfail,0xfff5
# ================================

// ================================
// register bank
// ================================
// bank 0
ldcl	sr,0x00
ldbiu	r0,0x00
ldbiu	r1,0x01
ldbiu	r2,0x02
ldbiu	r3,0x03
ldbiu	r4,0x04
ldbiu	r5,0x05
ldbiu	r6,0x06
ldbiu	r7,0x07
// bank 1
ldcl	sr,0x01
ldbiu	r0,0x10
ldbiu	r1,0x11
ldbiu	r2,0x12
ldbiu	r3,0x13
ldbiu	r4,0x14
ldbiu	r5,0x15
ldbiu	r6,0x16
ldbiu	r7,0x17
// bank 2
ldcl	sr,0x02
ldbiu	r0,0x20
ldbiu	r1,0x21
ldbiu	r2,0x22
ldbiu	r3,0x23
ldbiu	r4,0x24
ldbiu	r5,0x25
ldbiu	r6,0x26
ldbiu	r7,0x27
// bank 3
ldcl	sr,0x03
ldbiu	r0,0x30
ldbiu	r1,0x31
ldbiu	r2,0x32
ldbiu	r3,0x33
ldbiu	r4,0x34
ldbiu	r5,0x35
ldbiu	r6,0x36
ldbiu	r7,0x37

// check bank 0
ldcl	sr,0x00
cmpi	r0,0x00
movfc	r0,sr
cmpi	r1,0x01
movfc	r1,sr
and		r0,r1
cmpi	r2,0x02
movfc	r1,sr
and		r0,r1
cmpi	r3,0x03
movfc	r1,sr
and		r0,r1
cmpi	r4,0x04
movfc	r1,sr
and		r0,r1
cmpi	r5,0x05
movfc	r1,sr
and		r0,r1
cmpi	r6,0x06
movfc	r1,sr
and		r0,r1
cmpi	r7,0x07
movfc	r1,sr
and		r0,r1
movtc	sr,r0
beq		bank_pass1
ldwi	r7,lab_tstfail
jmp		r7
bank_pass1:
// check bank 1
ldcl	sr,0x01
cmpi	r0,0x10
movfc	r0,sr
cmpi	r1,0x11
movfc	r1,sr
and		r0,r1
cmpi	r2,0x12
movfc	r1,sr
and		r0,r1
cmpi	r3,0x13
movfc	r1,sr
and		r0,r1
cmpi	r4,0x14
movfc	r1,sr
and		r0,r1
cmpi	r5,0x15
movfc	r1,sr
and		r0,r1
cmpi	r6,0x16
movfc	r1,sr
and		r0,r1
cmpi	r7,0x17
movfc	r1,sr
and		r0,r1
movtc	sr,r0
beq		bank_pass2
ldwi	r7,lab_tstfail
jmp		r7
bank_pass2:
// check bank 2
ldcl	sr,0x02
cmpi	r0,0x20
movfc	r0,sr
cmpi	r1,0x21
movfc	r1,sr
and		r0,r1
cmpi	r2,0x22
movfc	r1,sr
and		r0,r1
cmpi	r3,0x23
movfc	r1,sr
and		r0,r1
cmpi	r4,0x24
movfc	r1,sr
and		r0,r1
cmpi	r5,0x25
movfc	r1,sr
and		r0,r1
cmpi	r6,0x26
movfc	r1,sr
and		r0,r1
cmpi	r7,0x27
movfc	r1,sr
and		r0,r1
movtc	sr,r0
beq		bank_pass3
ldwi	r7,lab_tstfail
jmp		r7
bank_pass3:
// check bank 3
ldcl	sr,0x03
cmpi	r0,0x30
movfc	r0,sr
cmpi	r1,0x31
movfc	r1,sr
and		r0,r1
cmpi	r2,0x32
movfc	r1,sr
and		r0,r1
cmpi	r3,0x33
movfc	r1,sr
and		r0,r1
cmpi	r4,0x34
movfc	r1,sr
and		r0,r1
cmpi	r5,0x35
movfc	r1,sr
and		r0,r1
cmpi	r6,0x36
movfc	r1,sr
and		r0,r1
cmpi	r7,0x37
movfc	r1,sr
and		r0,r1
movtc	sr,r0
beq		bank_pass4
ldwi	r7,lab_tstfail
jmp		r7
bank_pass4:

// ================================
tstpass:
ldwi	r0,simpass						// pass: LED=blue
bra		tstfnsh
tstfail:
ldwi	r0,simfail						// fail: LED=red
tstfnsh:
ldwi	r7,simfnsh
stw		[r7],r0
bra		pcnt-2
// ================================
